EDI8F32128C 128kx32 sram module 1 EDI8F32128C rev. 9 11/96 eco #7705 128kx32 static ram cmos, high speed module features 128kx32 bit cmos static random access memory ? access times bicmos: 10 and12ns cmos: 15, 20, 25, 35, 55, 70, 85 and 100ns ? individual byte selects ? fully static, no clocks ? ttl compatible i/o ? 2 volt data retention function (plcc package) high density package ? jedec standard pinouts ? 64 pad simm, no. 38 (10ns thru 35ns) ? 64 pin zip, no. 39 (10ns thru 35ns) ? 68 lead plcc (55ns thru 100ns) ? common data inputs and outputs single +5v ( 10%) supply operation pin configurations and block diagram the EDI8F32128C is a high speed 4 megabit static ram module organized as 128k words by 32 bits. this module is constructed from four 128kx8 static rams in soj or tsop packages on an epoxy laminate (fr4) board. four chip enables (e?-e3) are used to independently enable the four bytes. reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of enables. the EDI8F32128C is offered in 64 pin zip, 64 pad simm and 68 lead plcc packages, which enable four megabits of memory to be placed in less than 1.3 square inches of board space. all inputs and outputs are ttl compatible and operate from a single 5v supply. fully asynchronous circuitry requires no clocks or refreshing for operation and provides equal access and cycle times for ease of use. two pins, pd1 and pd2, are used to identify module memory density in applications where alternate modules can be interchanged. (zip and simm only) a low power version with 2 volt data retention functionality is also avail- able (plcc package only.) pd1 = open pd2 = open pin names a?-a16 address inputs e?-e3 chip enables w write enable g output enable dq?-dq31 common data input/output vcc power (+5v 10%) vss ground nc no connection a -a16 w g e e1 e2 e3 dq -dq7 dq8-dq15 dq16-dq23 dq24-dq31 17 8 8 8 8 vss pd2 dq8 dq9 dq10 dq11 a a1 a2 dq12 dq13 dq14 dq15 vss a15 e1 e3 nc g dq24 dq25 dq26 dq27 a3 a4 a5 vcc a6 dq28 dq29 dq30 dq31 pd1 dq dq1 dq2 dq3 vcc a7 a8 a9 dq4 dq5 dq6 dq7 w a14 e e2 a16 vss dq16 dq17 dq18 dq19 a10 a11 a12 a13 dq20 dq21 dq22 dq23 vss 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? electronic designs europe ltd. ? shelley house, the avenue ? lightwater, surrey gu18 5rf united kingdom ? 01276 472637 ? fax: 01276 473748 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 dq17 dq18 dq19 vss dq20 dq21 dq22 dq23 vcc dq24 dq25 dq26 dq27 vss dq28 dq29 dq30 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 dq14 dq13 dq12 vss dq11 dq10 dq9 dq8 vcc dq7 dq6 dq5 dq4 vss dq3 dq2 dq1 27 28 28 30 31 32 33 34 35 36 37 38 39 40 41 42 43 dq31 a6 a5 a4 a3 a2 a1 a vcc a13 a12 a11 a10 a9 a8 a7 dq 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 dq16 nc nc e3\ e2\ e1\ e \ nc vcc nc nc g\ w\ a16 a15 a14 dq15
2 EDI8F32128C rev. 9 11/96 eco #7705 EDI8F32128C 128kx32 sram module absolute maximum ratings* recommended dc operating conditions dc electrical characteristics parameter sym conditions min max max max units 10-20ns 25-35ns 55-100ns operating power icc1 w, e = vil, ii/o = 0ma, supply current min cycle 680 480 360 ma standby (ttl) power icc2 e 3 vih, vin vil or supply current vin 3 vih 120 112 80 ma full standby power icc3 e 3 vcc-0.2v c 40 20 5 ma supply current cmos vin 3 vcc-0.2v orvin 0.2v lp -- -- 400 m a input leakage current ili vin = 0v to vcc 20 20 20 m a output leakage current ilo v i/o = 0v to vcc 20 20 20 m a output high voltage voh ioh = -4.0ma( 35), or -1.0ma ( 3 55) 2.4 -- -- -- v output low voltage vol iol = 8.0ma( 35), or 2.1ma ( 3 55) -- 0.4 0.4 0.4 v *typical: ta = 25 c, vcc = 5.0v (f=1.0mhz, vin=vcc or vss) parameter sym max unit address lines ci 45 pf data lines cd/q 20 pf chip enable line cc 20 pf write line cn 45 pf ac test conditions input pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load 10-35ns 1ttl, cl = 30pf 55-100ns 1 ttl, cl=100pf voltage on any pin relative to vss -0.5v to 7.0v operating temperature ta (ambient) commercial. 0 c to +70 c industrial -40 c to +85 c storage temperature -55 c to +125 c power dissipation 4 watts output current. 20 ma parameter sym min typ max units supply voltage vcc 4.5 5.0 5.5 v supply voltage vss 0 0 0 v input high voltage vih 2.2 -- 6.0 v input low voltage vil -0.3 -- 0.8 v (note: for tehqz,tghqz and twlqz, cl = 5pf) e w g mode output power h x x standby high z icc2/icc3 l h l read dout icc1 l l x write din icc1 output l h h deselect high z icc1 these parameters are sampled, not 100% tested. *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance truth table
EDI8F32128C 128kx32 sram module 3 EDI8F32128C rev. 9 11/96 eco #7705 ac characteristics read cycle note 1: parameter guaranteed, but not tested. *bicmos read cycle 1 - w high, g, e low tavav tavqv tavqx data 2 a q address 1 address 2 data 1 tghqz telqv telqx e g q tehqz a tavav tglqv tglqx tavqv read cycle 2 - w high symbol 10ns* 12ns* 15ns 20ns 25ns parameter jedec alt. min max min max min max min max min max units read cycle time tavav trc 10 12 15 20 25 ns address access time tavqv taa 10 12 15 20 25 ns chip enable access telqv tacs 10 12 15 20 25 ns chip enable to output in low z (1) telqx tclz 3 3 3 3 3 ns chip disable to output in high z (1) tehqz tchz 5 6 8 10 12 ns output hold from address change tavqx toh 3 3 3 3 3 ns output enable to output valid tglqv toe 5 5 6 13 15 ns output enable to output in low z (1) tglqx tolz 0 0 0 0 0 ns output disable to output in high z(1) tghqz tohz 4 4 5 8 10 ns
4 EDI8F32128C rev. 9 11/96 eco #7705 EDI8F32128C 128kx32 sram module ac characteristics read cycle symbol 35ns 55ns 70ns 85ns 100ns parameter jedec alt. min max min max min max min max min max units read cycle time tavav trc 35 55 70 85 100 ns address access time tavqv taa 35 55 70 85 100 ns chip enable access telqv tacs 35 55 70 85 100 ns chip enable to output in low z (1) telqx tclz 3 5 5 5 5 ns chip disable to output in high z (1) tehqz tchz 15 30 30 35 40 ns output hold from address change tavqx toh 3 3 3 3 3 ns output enable to output valid tglqv toe 20 40 40 45 50 ns output enable to output in low z (1) tglqx tolz 0 0 0 0 0 ns output disable to output in high z(1) tghqz tohz 12 30 30 35 40 ns note 1: parameter guaranteed, but not tested. note 1: parameter guaranteed, but not tested. *bicmos ac characteristics write cycle symbol 10ns* 12ns* 15ns 20ns 25ns parameter jedec alt. min max min max min max min max min max units write cycle time tavav twc 10 12 15 20 25 ns chip enable to end of write telwh tcw 7 8 10 15 20 ns twleh tcw 7 8 10 15 20 ns address setup time tavwl tas 0 0 0 0 0 ns tavel tas 0 0 0 0 0 ns address valid to end of write tavwh taw 7 8 10 15 20 ns taveh taw 7 8 10 15 20 ns write pulse width twlwh twp 7 8 10 15 20 ns teleh twp 7 8 10 15 20 ns write recovery time twhax twr 0 0 0 0 0 ns tehax twr 0 0 0 0 0 ns data hold time twhdx tdh 3 3 3 3 3 ns tehdx tdh 3 3 3 3 3 ns write to output in high z (1) twlqz twhz 0 5 0 6 0 7 0 10 0 12 ns data to write time tdvwh tdw 5 6 7 12 15 ns tdveh tdw 5 6 7 12 15 ns output active from end of write (1) twhqx twlz 2 2 2 3 3 ns
EDI8F32128C 128kx32 sram module 5 EDI8F32128C rev. 9 11/96 eco #7705 symbol 35ns 55ns 70ns 85ns 100ns parameter jedec alt. min max min max min max min max min max units write cycle time tavav twc 35 55 70 85 100 ns chip enable to end of write telwh tcw 30 50 65 70 80 ns twleh tcw 30 50 65 70 80 ns address setup time tavwl tas 0 0 0 0 0 ns tavel tas 0 0 0 0 0 ns address valid to end of write tavwh taw 30 50 65 70 80 ns taveh taw 30 50 65 70 80 ns write pulse width twlwh twp 25 50 65 70 80 ns teleh twp 25 50 65 70 80 ns write recovery time twhax twr 0 0 0 0 0 ns tehax twr 0 0 0 0 0 ns data hold time twhdx tdh 3 0 0 0 0 ns tehdx tdh 3 0 0 0 0 ns write to output in high z (1) twlqz twhz 0 15 0 30 0 30 0 35 0 40 ns data to write time tdvwh tdw 20 30 30 35 40 ns tdveh tdw 20 30 30 35 40 ns output active from end of write (1) twhqx twlz 3 5 5 5 5 ns note 1: parameter guaranteed, but not tested. ac characteristics write cycle a e w d q tavav telwh tavwh twlwh tavwl tdvwh twhdx twhqx high z twlqz data valid twhax write cycle 1 - w controlled write cycle 2 - e controlled a w e d q tavav tavel tehax tdveh tehdx teleh taveh data valid high z twleh
6 EDI8F32128C rev. 9 11/96 eco #7705 EDI8F32128C 128kx32 sram module data retention - e controlled characteristic sym test conditions vdd min typ max unit 70 c 80 c data retention voltage vdd vdd = 0.2v 2 -- -- -- v data retention quiescent current iccdr e 3 vdd -0.2v 2v -- 10 125 185 m a vin 3 vdd -0.2v 3v -- 20 200 250 m a chip disable to data retention time (1) tcdr or vin 0.2v 0 -- -- -- ns operation recovery time (1) tr 5 -- -- -- ns note 1: parameter guaranteed, but not tested. data retention characteristics data retention mode e 3 vdd -0.2v e vcc tcdr tr 4.5v 4.5v vdd part number speed package (ns) no. bicmos edi8f32128b10mzc 10 39 edi8f32128b12mzc 12 39 cmos EDI8F32128C15mzc 15 39 EDI8F32128C20mzc 20 39 EDI8F32128C25mzc 25 39 EDI8F32128C35mzc 35 39 part number speed package (ns) no. bicmos edi8g32128b10mmc 10 38 edi8g32128b12mmc 12 38 cmos EDI8F32128C15mmc 15 38 EDI8F32128C20mmc 20 38 EDI8F32128C25mmc 25 38 EDI8F32128C35mmc 35 38 EDI8F32128C55bac 55 328 EDI8F32128C70bac 70 328 EDI8F32128C85bac 85 328 EDI8F32128C100bac 100 328 edi8f32128lp55bac 55 328 edi8f32128lp70bac 70 328 edi8f32128lp85bac 85 328 edi8f32128lp100bac 100 328 edi8f32128lp-bac note: 1. for gold simm, change edi8f to edi8g. 2. the bicmos 10 & 12ns simms availabv2le with gold contacts only. ordering information
EDI8F32128C 128kx32 sram module 7 EDI8F32128C rev. 9 11/96 eco #7705 package description package no. 328 64 pin plcc package no. 38 64 lead simm package no. 39 64 pin zip plastic 0.600 max 3.584 0.050 typ 0.208 max 0.250 0.400 0.250 p64 0.62r 3.855 3.845 p1 0.125 dia. typ. (2 plcs.) .125 min .050 .050 .170 .130 .017 typ. typ. .175 .580 .050 .100 .250 typ. .021 .125 max. .240 .100 typ. max. 3.665 max.
8 EDI8F32128C rev. 9 11/96 eco #7705 EDI8F32128C 128kx32 sram module electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? electronic designs europe ltd. ? shelley house, the avenue ? lightwater, surrey gu18 5rf united kingdom ? 01276 472637 ? fax: 01276 473748 electronic designs inc. reserves the right to change specifications without notice. cage no. 66301
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